DATE:  Monday, August 21
                       TIME:  13:00-14:00
                       PLACE: A3017 (CDT Demo Room)
          VLSI Architectures for Multitier Wireless Systems
                         Joseph R. Cavallaro
                Center for Multimedia Communication
                Dept. of Electrical and Computer Eng.
                 Rice University, Houston, TX 77005.


Next-generation computing systems will be highly integrated using
wireless networking. The Rice Everywhere NEtwork (RENE) project is
exploring the integration of WCDMA cellular systems, high speed
wireless LANs, and home wireless networks to produce a seamless
multitier network interface. We are currently developing a simulation
acceleration testbed and a multitier network interface card (mNIC)
consisting of DSP processors, custom VLSI ASICs, and FPGAs for
baseband signal processing to interact with the various RF units and
the host processor. This testbed will also allow us to explore high
performance algorithm alternatives through computer aided design tools
for rapid prototyping and hardware/software co-design of embedded
Proposed baseband algorithms for Third Generation WCDMA communication
systems and beyond have extremely high performance requirements. In
this talk, we discuss the implementation issues involved for one of
the proposed multiuser channel estimation and detection algorithms for
the uplink in base-stations using the Texas Instruments TMS320C62 and
TMS320C67 DSP processors. We also present an algorithm refinement to
the multistage detector and a prototype VLSI implementation of the
detector for the WCDMA uplink which can be scaled to larger systems.
Joseph R. Cavallaro received the Ph.D. degree from Cornell University,
Ithaca, NY, in 1988. He is with Rice University in Houston, Texas,
where he is currently an Associate Professor in the Department of
Electrical and Computer Engineering and Associate Director of the
Center for Multimedia Communication.
Dr. Cavallaro served as Program Director in the Prototyping Tools and
Methodology program in the MIPS Division at NSF during 1996-1997.  His
research interests include computer arithmetic, fault tolerance, VLSI
design and microlithography, and VLSI/DSP architectures and algorithms
for wireless communication systems. He can be reached at or