We use the MIPS gcc crosscompiler from www.mips.com, sde lite edition. See below for a short summary of the assembly opcodes.
     NATIVE MIPS OPCODES

     ADD       rd rs rt         # rd := rs + rt,       overflow will trap
     ADDI      rt rs expr       # rt := rs + SX(expr), overflow will trap
     ADDU      rd rs rt         # rd := rs + rt,       no trap on overflow
     ADDIU     rt rs expr       # rt := rs + SX(expr), no trap on overflow
     AND       rd rs rt         # rd := rs & rt
     ANDI      rt rs expr       # rt := rs & ZX(expr)
     BEQ       rs rt label      # branch if contents rs equals rt's
     BGEZ      rs    label      # branch if contents rs >= 0
     BGEZAL    rs    label      # branch if contents rs >= 0, link reg 31
     BGTZ      rs    label      # branch if contents rs > 0
     BLEZ      rs    label      # branch if contents rs <= 0
     BLTZ      rs    label      # branch if contents rs < 0
     BLTZAL    rs    label      # branch if contents rs < 0, link reg 31
     BNE       rs rt label      # branch if contents rs not equal to rt's
     JALR      rd rs            # branch to address in rs, link to reg rd
     JR           rs            # branch to address in rs
     LB        rt    addr       # load byte, sign-extended
     LBU       rt    addr       # load byte, zero-extended
     LH        rt    addr       # load halfword, sign-extended
     LHU       rt    addr       # load halfword, zero-extended
     LUI       rt    expr       # rt := (expr shifted left 16 bits)
     LW        rt    addr       # load 32-bit word, word-aligned
     MFC0      rt rd            # (kernel mode) rt := (CP0:rd)
     MTC0      rt rd            # (kernel mode) (CP0:rd) := rt
     NOP                        # no operation
     NOR       rd rs rt         # rd := ~( rs | rt )
     OR        rd rs rt         # rd :=    rs | rt
     ORI       rt rs expr       # rt :=    rs | ZX(expr)
     RFE                        # return from exception (kernel mode)
     SB        rt    addr       # store 8-bit byte
     SH        rt    addr       # store 16-bit halfword, halfword-aligned
     SLL       rd rt expr       # rd := rt logical-shifted-left expr bits
     SLLV      rd rt rs         # rd := rt logical-shifted-left by value in rs
     SLT       rd rs rt         # rd := rs < rt, signed
     SLTI      rt rs expr       # rt := rs < SX(expr), signed
     SLTIU     rt rs expr       # rt := rs < SX(expr), unsigned (yes, SX)
     SLTU      rd rs rt         # rd := rs < rt, unsigned
     SRA       rd rt expr       # rd := rt arith-rightshifted expr bits
     SRAV      rd rt rs         # rd := rt arith-rightshifted by val in rs
     SRL       rd rt expr       # rd := rt logical-rightshifted expr bits
     SRLV      rd rt rs         # rd := rt logical-rightshifted by val in rs
     SUB       rd rs rt         # rd := rs - rt,       overflow will trap
     SUBU      rd rs rt         # rd := rs - rt,       no trap on overflow
     SW        rt    addr       # store 32-bit word, word-aligned
     SYSCALL                    # trap to supervisor
     XOR       rd rs rt         # rd := rs ^ rt
     XORI      rt rs expr       # rt := rs ^ ZX(expr)

  note:     SLLV, SRAV, SRLV   shift amount is l.o. 5 bits of reg rs


     SOME PSEUDO-OPCODES

     ABS       rd rs            # rd := abs(rs), trap on 0x80000000
     B               label      # unconditional branch
     BAL             label      # unconditional branch-and-link,  reg 31
     JALR         rs            # branch to address in rs, link to reg 31
     MOVE      rd rs            # rd := rs
     NEG       rd rs            # rd := - rs, trap on 0x80000000
     NEGU      rd rs            # rd := - rs, no trap
     NOT       rd rs            # rd := ~ rs 
     LA        rt    label      # rt := symbolic value of label
     LI        rt    expr       # rt := expr
     ROL       rd rt rs         # rd := rt rotated-left by value in rs
     ROR       rd rt rs         # rd := rt rotated-right by value in rs
Last modified 2005-04-12