Welcome to Computer Organization and Logic Design lp4 2006

Computer Organization and Logic Design gives a broad introduction to modern computer architecture with a focus on embedded systems. The course primary target the hardware/software interface, where the realms of logic design, computer architecture and programming meets. Aspects of data representation, computer arithmetic, memory hierarchy and i/o are covered and the concept of operating system is introduced. Exercises and assignments deal with logic and architecture design, low-level programming, operating system implementation and the relation between low and higher level languages. The course is a prerequisite for Computer Architecture SMD150.


Date News
2006-05-31 To get bonus points from lab3 part 3, you must submit the lab before the exam. (Actual Lab presentation may be done later.)
2006-05-22 Some recent old exams can be found in exams. No "official" answers are given, try solve the assignments, if you have any specific questions, write me (Per) a mail, and I'll have a go at it.
2006-05-15 If you are missing the linker script for lab5, please re-run the install script.
2006-05-11 The lectures section is now updated with chapter annotations and reading advices. Sections marked (overview) can be read in less detail. Some chapters from the book is left out, some addational meterial has been added (reference documentation, slides etc.).
2006-05-11 The BD bit (bit31 of the CP0 Cause register) is not implemented in the MIPS 2.0 model. Instead if an interrupt occurs in the branch delay slot the simulator will set the EPC register to the preceding branch, as shown below;
EPC --->  beq  $a0, $t0, restart1
          nop                      <--- Timer interrupt
2006-05-05 Some of you have noticed that "rewind" (stepping backwards) does not operate correctly for the I/O devices (i.e., timer and keyboard). We are aware of the problem, but we do not plan to fix it until some other internal issues in SyncSim have first been attended.
2006-05-05 On Tuesday's lecture I will review lab3-part2, each group will revist their lab after the lecture and make a re-submit on lab3-part2.

For the coding of the SLT instruction please use the following lab3_2_test.s, insert your code under the label myslt. The test program should eventually enter the ok8 loop, if entering the error loop, you have an error in your code. Please look at the structure of the test program, first stressing the simple cases, then forcing overflow to be generated. Since exhaustive testing is untractable for such problems, one has to rely on test cases. Generating good test vectors (cases) is crucial to validating the quality of your code. Testing and testgeneration make out for a very large portion (maybe even dominating part) of industrial code development. Scrutinize the test code, maybe I have forgotten/left out some important test vectors!!!!
2006-04-21 Please re-run the install script, we have updated the lab3 Makefile;
2006-04-07 SyncSim homepage; additional information on the SyncSim project, http://bart.sm.luth.se/~andkro-2/syncsim/
2006-04-07 If you do not get a reply from the lab automata when submitting a lab, it is due to a bug in the mail handler (it will crash if your submitted mail holds long lines). Please cut long lines and try again.
2006-04-07 ON POPUPLAR DEMAND, lab deadlines are propsoned until Wednesday noons (12.00), e.g. 2006-04-10 into 2006-04-12.
2006-04-05 Deadlines for labs now posted (see Laborations). Lab1 due, 2006-04-10, 12.00.
2006-03-24 To install and run the SyncSim simulator, see the instructions found under the SyncSim menu to the left.
2006-03-23 Welcome to all students taking smd137! News section up and running for lp4 2006. Yes! You can now ENROLL, see general info on how to do it. After you have all ENROLLED (please do so before the third lecture) the Lab status page (see menu) will be updated and there you will get your unique lab group number. You may start earlier - grab any group specific lab assignment, all are very much similar, just to start reading more about the lab, when your group number comes up, grab your specific lab assigment.

Course Staff

Per Lindgren Per.Lindgren@ltu.se Office: A2303 (Teacher and examiner for the course)

Course Material

Besides the literature (see below) course material will be distributed through this web page; lecture planning/slides, reading advice, laborations etc.
Click to enlarge Main text
David A. Patterson, John L. Hennessy, Peter J. Ashenden, James R. Larus, Daniel J. Sorin
Computer Organization and Design: The Hardware/Software Interface, Third Edition
Morgan Kaufmann; 3 edition (August 2, 2004) ISBN: 1558606041